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dc.contributor.authorWang, Yu-Yun
dc.contributor.authorWang, Kuan-Chi
dc.contributor.authorChang, Ting -Yu
dc.contributor.authorRonchi, Nicolo
dc.contributor.authorO'Sullivan, Barry
dc.contributor.authorBanerjee, Kaustuv
dc.contributor.authorVan den Bosch, Geert
dc.contributor.authorVan Houdt, Jan
dc.contributor.authorWu, Tian-Li
dc.date.accessioned2023-03-09T14:37:03Z
dc.date.available2022-12-30T03:10:10Z
dc.date.available2023-03-09T14:37:03Z
dc.date.issued2022
dc.identifier.issn0026-2714
dc.identifier.otherWOS:000896862600011
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/40921.2
dc.sourceWOS
dc.titleRelaxation analysis to understand positive bias induced trapping in ferroelectric FETs with Si and Gd dopants
dc.typeJournal article
dc.contributor.imecauthorRonchi, Nicolo
dc.contributor.imecauthorO'Sullivan, Barry
dc.contributor.imecauthorBanerjee, Kaustuv
dc.contributor.imecauthorVan den Bosch, Geert
dc.contributor.imecauthorVan Houdt, Jan
dc.contributor.orcidimecRonchi, Nicolo::0000-0002-7961-4077
dc.contributor.orcidimecO'Sullivan, Barry::0000-0002-9036-8241
dc.contributor.orcidimecBanerjee, Kaustuv::0000-0001-8003-6211
dc.contributor.orcidimecVan Houdt, Jan::0000-0003-1381-6925
dc.contributor.orcidimecVan den Bosch, Geert::0000-0001-9971-6954
dc.identifier.doi10.1016/j.microrel.2022.114680
dc.source.numberofpages7
dc.source.peerreviewyes
dc.source.beginpage114680
dc.source.endpagena
dc.source.journalMICROELECTRONICS RELIABILITY
dc.source.issuena
dc.source.volume138
imec.availabilityPublished - imec
dc.description.wosFundingTextThis work was financially supported by the "Center for the Semi-conductor Technology Research" from The Featured Areas Research Center Program within the framework of the Higher Education Sprout Project by the Ministry of Education (MOE) in Taiwan. Also supported in part by the National Science and Technology Conucil (NSTC), under Grant 111-2634-F-A49-008, 111-2622-8-A49-018-SB, and the Young Scholar Fellowship Program under Grant 111-2636-E-A49-012.


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