The design of non-stacked and symmetric XOR for high-speed applications

Abstract

The paper proposes an advanced exclusive-OR (XOR) design using a non-stacked symmetric structure based on complementary pass transistor logic (CPL) for high-speed applications. The proposed XOR adopts a non-stacked structure where a cascade structure is used for pull-up/down paths instead of a cascoded structure, allowing the increase of pull-up/down strength and thus faster output transitions. The CPL provides a symmetric scheme that further improves the bandwidth by eliminating the deterministic jitter generated from various input patterns. Verified in a 28-nm CMOS process, the proposed XOR shows 17.2 times smaller data-dependent jitter compared to the conventional XOR at the data rate near the limit bandwidth of the process.