dc.contributor.author | Silva, V. C. P. | |
dc.contributor.author | Martino, J. A. | |
dc.contributor.author | Simoen, Eddy | |
dc.contributor.author | Veloso, Anabela | |
dc.contributor.author | Agopian, P. G. D. | |
dc.date.accessioned | 2024-04-10T09:36:32Z | |
dc.date.available | 2023-10-15T17:21:19Z | |
dc.date.available | 2024-04-10T09:36:32Z | |
dc.date.issued | 2023 | |
dc.identifier.issn | 0038-1101 | |
dc.identifier.other | WOS:001071308100001 | |
dc.identifier.uri | https://imec-publications.be/handle/20.500.12860/42758.2 | |
dc.source | WOS | |
dc.title | Evaluation of n-type gate-all-around vertically-stacked nanosheet FETs from 473 K down to 173 K for analog applications | |
dc.type | Journal article | |
dc.contributor.imecauthor | Simoen, Eddy | |
dc.contributor.imecauthor | Veloso, Anabela | |
dc.contributor.orcidimec | Simoen, Eddy::0000-0002-5218-4046 | |
dc.identifier.doi | 10.1016/j.sse.2023.108729 | |
dc.source.numberofpages | 5 | |
dc.source.peerreview | yes | |
dc.source.beginpage | Art. 108729 | |
dc.source.endpage | N/A | |
dc.source.journal | SOLID-STATE ELECTRONICS | |
dc.source.issue | October | |
dc.source.volume | 208 | |
imec.availability | Published - imec | |
dc.description.wosFundingText | The authors acknowledge CNPq and CAPES for the financial support. The devices have been processed in the frame of imecs Core Partner Program on Logic Devices.~ | |