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dc.contributor.authorSilva, V. C. P.
dc.contributor.authorMartino, J. A.
dc.contributor.authorSimoen, Eddy
dc.contributor.authorVeloso, Anabela
dc.contributor.authorAgopian, P. G. D.
dc.date.accessioned2024-04-10T09:36:32Z
dc.date.available2023-10-15T17:21:19Z
dc.date.available2024-04-10T09:36:32Z
dc.date.issued2023
dc.identifier.issn0038-1101
dc.identifier.otherWOS:001071308100001
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/42758.2
dc.sourceWOS
dc.titleEvaluation of n-type gate-all-around vertically-stacked nanosheet FETs from 473 K down to 173 K for analog applications
dc.typeJournal article
dc.contributor.imecauthorSimoen, Eddy
dc.contributor.imecauthorVeloso, Anabela
dc.contributor.orcidimecSimoen, Eddy::0000-0002-5218-4046
dc.identifier.doi10.1016/j.sse.2023.108729
dc.source.numberofpages5
dc.source.peerreviewyes
dc.source.beginpageArt. 108729
dc.source.endpageN/A
dc.source.journalSOLID-STATE ELECTRONICS
dc.source.issueOctober
dc.source.volume208
imec.availabilityPublished - imec
dc.description.wosFundingTextThe authors acknowledge CNPq and CAPES for the financial support. The devices have been processed in the frame of imecs Core Partner Program on Logic Devices.~


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