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The spacer/replacer concept: a viable route for sub-100 nm ultrathin-film fully-depleted SOI CMOS

dc.contributor.authorvan Meer, Hans
dc.contributor.authorDe Meyer, Kristin
dc.date.accessioned2021-10-14T23:38:03Z
dc.date.available2021-10-14T23:38:03Z
dc.date.issued2002
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/6953
dc.sourceIIOimport
dc.titleThe spacer/replacer concept: a viable route for sub-100 nm ultrathin-film fully-depleted SOI CMOS
dc.typeJournal article
dc.contributor.imecauthorDe Meyer, Kristin
dc.source.peerreviewno
dc.source.beginpage46
dc.source.endpage48
dc.source.journalIEEE Electron Device Letters
dc.source.issue1
dc.source.volume23
imec.availabilityPublished - imec


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