Browsing by author "Markulic, Nereo"
Now showing items 1-20 of 27
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A 1-MS/s to 1-GS/s Ringamp-Based Pipelined ADC With Fully Dynamic Reference Regulation and Stochastic Scope-on-Chip Background Monitoring in 16 nm
Hershberg, Benjamin; Markulic, Nereo; Lagos Benites, Jorge; Martens, Ewout; Dermit, Davide; Craninckx, Jan (2021) -
A 10-bit, 550-fs step digital-to-time converter in 28nm CMOS
Markulic, Nereo; Raczkowski, Kuba; Wambacq, Piet; Craninckx, Jan (2014) -
A 10.1 ENOB, 6.2fJ/con.-step, 500MS/s ringamp-based pipelined-SAR ADC with background calibration and dynamic reference regulation in 16nm CMOS
Lagos Benites, Jorge; Markulic, Nereo; Hershberg, Benjamin; Dermit, Davide; Shrivas, Mithlesh; Martens, Ewout; Craninckx, Jan (2021) -
A 10.1-ENOB, 6.2-fJ/conv.-step, 500-MS/s, Ringamp-Based Pipelined-SAR ADC With Background Calibration and Dynamic Reference Regulation in 16-nm CMOS
Lagos Benites, Jorge; Markulic, Nereo; Hershberg, Benjamin; Dermit, Davide; Shrivas, Mithlesh; Martens, Ewout; Craninckx, Jan (2022) -
A 12-bit 1GS/s ADC With Background Distortion and Split-ADC-Like Gain Calibration
Wei, Lai; Zheng, Zihao; Markulic, Nereo; Lagos, Jorge; Martens, Ewout; Martins, Rui Paulo; Zhu, Yan; Craninckx, Jan; Chan, Chi-Hang (2023) -
A 12mW 10 GHz FMCW PLL based on an integrating DAC with 28 kHz rms-frequency-error for 23 MHz/ s slope and 1.2 GHz chirp-bandwidth
Renukaswamy, Pratap; Markulic, Nereo; Wambacq, Piet; Craninckx, Jan (2020) -
A 12mW 10GHz FMCW PLL based on an integrating DAC with 90kHz rms frequency error for 23MHz/µs slope and 1.2GHz chirp bandwidth
Renukaswamy, Pratap; Markulic, Nereo; Park, Sehoon; Kankuppe Raghavendra Swamy, Anirudh Praveen; Wambacq, Piet; Craninckx, Jan (2020) -
A 16-GHz Background-Calibrated Duty-Cycled FMCW Charge-Pump PLL
Renukaswamy, Pratap; Vaesen, Kristof; Markulic, Nereo; Craninckx, Jan (2024) -
A 1MS/s to 1GS/s Ringamp-Based Pipelined ADC with Fully Dynamic Reference Regulation and Stochastic Scope-on-Chip Background Monitoring in 16nm
Hershberg, Benjamin; Markulic, Nereo; Craninckx, Jan; Lagos Benites, Jorge; Martens, Ewout; Dermit, Davide (2020) -
A 3.2GS/s 10 ENOB 61mW ringamp ADC in 16nm with background monitoring of distortion
Hershberg, Benjamin; Martens, Ewout; van Liempd, Barend; Craninckx, Jan; Markulic, Nereo; Lagos Benites, Jorge; Dermit, Davide (2019) -
A 4-GS/s 10-ENOB 75-mW Ringamp ADC in 16-nm CMOS With Background Monitoring of Distortion
Hershberg, Benjamin; Dermit, Davide; van Liempd, Barend; Martens, Ewout; Markulic, Nereo; Lagos Benites, Jorge; Craninckx, Jan (2021) -
A 5.5 GHz background-calibrated subsampling polar transmitter with -41.3 dB EVM at 1024 QAM in 28nm CMOS
Markulic, Nereo; Renukaswamy, Pratap; Martens, Ewout; van Liempd, Barend; Wambacq, Piet; Craninckx, Jan (2018) -
A 5.5 GHz background-calibrated subsampling polar transmitter with -41.3 dB EVM at 1024 QAM in 28-nm CMOS
Markulic, Nereo; Renukaswamy, Pratap; Martens, Ewout; van Liempd, Barend; Wambacq, Piet; Craninckx, Jan (2019) -
A 6-to-600MS/s fully dynamic ringamp pipelined ADC with asynchronous event-driven clocking in 16nm
Hershberg, Benjamin; van Liempd, Barend; Martens, Ewout; Craninckx, Jan; Markulic, Nereo; Dermit, Davide; Lagos Benites, Jorge (2019) -
A 9.2-12.7GHz wideband fractional-N subsampling PLL in 28nm CMOS with 280fs RMS jitter
Raczkowski, Kuba; Markulic, Nereo; Hershberg, Benjamin; Van Driessche, Joris; Craninckx, Jan (2014) -
A 9.2–12.7GHz wideband fractional-N subsampling PLL in 28nm CMOS with 280fs RMS jitter
Raczkowski, Kuba; Markulic, Nereo; Hershberg, Benjamin; Craninckx, Jan (2015) -
A DTC-based subsampling PLL capable of self- calibrated fractional synthesis and two-point modulation
Markulic, Nereo; Raczkowski, Kuba; Martens, Ewout; Paro Filho, Pedro; Hershberg, Benjamin; Wambacq, Piet; Craninckx, Jan (2016) -
A Fractional-n subsampling PLL based on a digital-to-time converter
Markulic, Nereo; Raczkowski, Kuba; Wambacq, Piet; Craninckx, Jan (2016) -
A self-calibrated 10 Mb/s phase modulator with -37.4 dB EVM based on a 10.1-12.4 GHz, -246.6 dB FoM fractional-N subsampling PLL
Markulic, Nereo; Raczkowski, Kuba; Martens, Ewout; Paro Filho, Pedro; Hershberg, Benjamin; Wambacq, Piet; Craninckx, Jan (2016) -
A self-calibrated 16-GHz subsampling-PLL-based fast-chirp FMCW modulator with 1.5GHz bandwidth
Shi, Qixian; Bunsen, Keigo; Markulic, Nereo; Craninckx, Jan (2019)