Browsing by author "Venezia, Vincent"
Now showing items 1-4 of 4
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CMOS scaling beyond the 90 nm CMOS technology node: shallow junction and integration challenges
Dachs, Charles; Surdeanu, Radu; Pawlak, Bartek; Doornbos, Gerben; Duffy, R.; Heringa, Anco; Ponomarev, Youri; Venezia, Vincent; Van Dal, Mark; Stolk, P.; Lindsay, Richard; Henson, Kirklen; Dieu, B.; Geenen, Luc; Hoflijk, Ilse; Richard, Olivier; Clarysse, Trudo; Brijs, Bert; Vandervorst, Wilfried; Pagès, Xavier (2003) -
Enhanced low temperature electrical activation of B in Si
Kalyanaraman, R.; Venezia, Vincent; Pelaz, L.; Haynes, T.E.; Gossmann, H.J.L.; Rafferty, C.S. (2003) -
Gate dielectrics for high performance and low power CMOS SoC applications
Cubaynes, Florence; Dachs, Charles; Detcheverry, Celine; Zegers, A.; Venezia, Vincent; Schmitz, Jurriaan; Stolk, Peter; Jurczak, Gosia; Henson, Kirklen; Degraeve, Robin; Rothschild, Aude; Conard, Thierry; Pétry, Jasmine; Da Rold, Martina; Schaekers, Marc; Badenes, Gonçal; Date, L.; Pique, D.; Al-Shareef, H.; Murto, R. (2002) -
The RF potential of high-performance 100nm CMOS technology
Venezia, Vincent; Scholten, A.J.; Detcheverry, Celine; Boots, Henk; Jeamsaksiri, Wutthinan; Grau, Lluis; Klaassen, D.B.M.; Velghe, Rudolf; Havens, R.J.; Tiemeijer, Luuk (2002)