Now showing items 1-2 of 2

    • Buried Bitline for sub-5nm SRAM Design 

      Mathur, R.; Bhargava, M.; Annamalai, S.; Chong, Y. K.; Sinha, S.; Cline, B.; Kulkarni, J. P.; Salahuddin, Shairfe Muhammad; Schuddinck, Pieter; Ryckaert, Julien; Gupta, Anshul (2020)
    • Buried Interconnects for Sub-5 nm SRAM Design 

      Mathur, R.; Bhargava, M.; Cline, B.; Salahuddin, Shairfe Muhammad; Gupta, Anshul; Schuddinck, Pieter; Ryckaert, Julien; Kulkarni, J.P. (2022)