Browsing by author "Balachandran, Jayaprakash"
Now showing items 1-10 of 10
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Above-IC interconnects for high speed digital integrated circuits
Balachandran, Jayaprakash (2007-07) -
Accurate broadband parameter extraction methodology for S-parameter measurements
Balachandran, Jayaprakash; Brebels, Steven; Carchon, Geert; De Raedt, Walter; Nauwelaers, Bart; Beyne, Eric (2005) -
Accurate Extraction of Time Domain Performance through Windowless Transforms
Balachandran, Jayaprakash; Chandrasekhar, Arun; Beyne, Eric; De Raedt, Walter; Nauwelaers, Bart (2003) -
Characterisation, modelling and design of bond-wire interconnects for chip-package co-design
Chandrasekhar, Arun; Stoukatch, Serguei; Brebels, Steven; Balachandran, Jayaprakash; Beyne, Eric; De Raedt, Walter; Nauwelaers, Bart; Podddar, Anindya (2003) -
Compact broadband resistance model for microstrip transmission lines
Balachandran, Jayaprakash; Brebels, Steven; Carchon, Geert; De Raedt, Walter; Nauwelaers, Bart; Beyne, Eric (2004) -
Extending on-die wiring hierarchy with wafer-level packaging concepts
Balachandran, Jayaprakash; Brebels, Steven; Carchon, Geert; Webers, Tomas; De Raedt, Walter; Nauwelaers, Bart; Beyne, Eric (2004) -
Factors involved in performance optimisation of GHz chip-package co-design
Chandrasekhar, Arun; Brebels, Steven; Rottenberg, Xavier; Vandevelde, Bart; Driessens, Evelien; Balachandran, Jayaprakash; Beyne, Eric; De Raedt, Walter; Nauwelaers, Bart; Mertens, Robert (2004-11) -
Package level interconnect options
Balachandran, Jayaprakash; Brebels, Steven; Carchon, Geert; Webers, Tomas; De Raedt, Walter; Nauwelaers, Bart; Beyne, Eric (2005) -
Packaging approach for nano-CMOS wiring
Balachandran, Jayaprakash; Brebels, Steven; Carchon, Geert; De Raedt, Walter; Nauwelaers, Bart; Beyne, Eric (2005-06) -
Time domain performance of leadless CSPs extracted from scattering parameter measurements and circuit models
Chandrasekhar, Arun; Balachandran, Jayaprakash; Beyne, Eric; De Raedt, Walter; Nauwelaers, Bart (2003)