Browsing by author "Milojevic, Dragomir"
Now showing items 1-20 of 32
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2D vs 3D integration: Architecture-technology co-design for future mobile MPSoC platforms
Agrawal, Prashant; Milojevic, Dragomir; Raghavan, Praveen; Catthoor, Francky; Van der Perre, Liesbet; Beyne, Eric; Varadarajan, Ravi (2014) -
3-D Integration from system design perspective
Milojevic, Dragomir; Van der Plas, Geert (2009) -
3D SoC integration, beyond 2.5D chiplets
Beyne, Eric; Milojevic, Dragomir; Van der Plas, Geert; Beyer, Gerald (2021) -
3D-convolution based fast transient thermal model for 3D integrated circuits: methodology and applications
Maggioni, Federica; Oprins, Herman; Milojevic, Dragomir; Beyne, Eric; De Wolf, Ingrid; Baelmans, Martine (2015) -
3D-optimized SRAM Macro Design and Application to Memory-on-Logic 3D-IC at Advanced Nodes
Chen, Rongmei; Weckx, Pieter; Salahuddin, Shairfe Muhammad; Kim, Soon-Wook; Sisto, Giuliano; Van der Plas, Geert; Stucchi, Michele; Baert, Rogier; Debacker, Peter; Na, Myung Hee; Ryckaert, Julien; Milojevic, Dragomir; Beyne, Eric (2020) -
3D-stacked integrated circuits: design consequences, architectural aspects, design methodologies and tools
Milojevic, Dragomir; Van der Plas, Geert (2009) -
An analytical compact model for estimation of stress in multiple through-silicon via configurations
Eneman, Geert; Cho, Jong Hoon; Moroz, Victor; Milojevic, Dragomir; Choi, Munkang; De Meyer, Kristin; Mercha, Abdelkarim; Beyne, Eric; Hoffmann, Thomas Y.; Van der Plas, Geert (2011) -
Automated PathFinding tool chain for 3D-stacked integrated circuits: practical case study
Milojevic, Dragomir; Carlson, Trevor; Croes, Kris; Radojcic, Riko; Ragett, D.F.; Seynhaeve, D.; Van der Plas, Geert; Marchal, Pol (2009-09) -
Concepts and implementation of spatial division multiplexing for guaranteed throughput in networks-on-chip
Leroy, Anthony; Milojevic, Dragomir; Verkest, Diederik; Robert, F.; Catthoor, Francky (2008-09) -
Cost-performance optimisation of fine-pitch W2W bonding: functional system partitioning with heterogeneous FEOL/BEOL configurations
Milojevic, Dragomir; Van der Plas, Geert; Beyne, Eric; Debacker, Peter; Wang, Jane; Kim, Ryan Ryoung han; Velenis, Dimitrios (2020) -
Design and Optimization of SRAM Macro and Logic Using Backside Interconnects at 2nm node
Chen, Rongmei; Sisto, Giuliano; Jourdain, Anne; Hiblot, Gaspard; Stucchi, Michele; Kakarla, Naveen; Chehab, Bilal; Salahuddin, Shairfe Muhammad; Schleicher, Filip; Veloso, Anabela; Hellings, Geert; Weckx, Pieter; Milojevic, Dragomir; Van der Plas, Geert; Ryckaert, Julien; Beyne, Eric (2021) -
Design And Sign-off Methodologies For Wafer-To-Wafer Bonded 3D-ICs At Advanced Nodes (invited)
Sisto, Giuliano; Chen, Rongmei; Chou, Richard; Van der Plas, Geert; Beyne, Eric; Rod Metcalfe; Milojevic, Dragomir (2021-11-04) -
Design Enablement of 3-Dies Stacked 3D-ICs Using Fine-Pitch Hybrid-Bonding and TSVs
Naeim, Mohamed; Yang, Hanqi; Chen, Pinhong; Bao, Rong; Dekeyser, Antoine; Sisto, Giuliano; Brunion, Moritz; Chen, Rongmei; Van der Plas, Geert; Beyne, Eric; Milojevic, Dragomir (2023) -
Design enablement of fine pitch face-to-face 3D system integration using die-by-die place & route
Sisto, Giuliano; Chou, Richard; Milojevic, Dragomir (2019) -
Design issues in heterogeneous 3D/2.5D integration
Milojevic, Dragomir; Marchal, Pol; Marinissen, Erik Jan; Van der Plas, Geert; Verkest, Diederik; Beyne, Eric (2013-01) -
Evaluation of Nanosheet and Forksheet Width Modulation for Digital IC Design in the Sub-3 nm Era
Sisto, Giuliano; Zografos, Odysseas; Chehab, Bilal; Kakarla, Naveen; Xiang, Yang; Milojevic, Dragomir; Weckx, Pieter; Hellings, Geert; Ryckaert, Julien (2022) -
High-Performance Logic-on-Memory Monolithic 3-D IC Designs for Arm Cortex-A Processors
Zhu, Lingjun; Bamberg, Lennart; Pentapati, Sai Surya Kiran; Chang, Kyungwook; Catthoor, Francky; Milojevic, Dragomir; Cline, Brian; Sinha, Saurabh; Xu, Xiaoqing; Garcia-Ortiz, Alberto; Lim, Sung Kyu (2021) -
How much cost reduction justifies the adoption of monolithic 3D ICs at 7nm node?
Ku, Bon Woong; Debacker, Peter; Milojevic, Dragomir; Raghavan, Praveen; Lim, Sung Kyu (2016) -
IR-Drop Analysis of Hybrid Bonded 3D-ICs with Backside Power Delivery and mu- & n- TSVs
Genneret, B.; Chou, R.; Sisto, Giuliano; Chehab, Bilal; Baert, Rogier; Chen, Rongmei; Weckx, Pieter; Ryckaert, Julien; Van der Plas, Geert; Beyne, Eric; Milojevic, Dragomir (2021) -
IR-drop aware design and Technology co-optimization for N5 node with different device and cell height options
Mattii, Luca; Milojevic, Dragomir; Debacker, Peter; Sherazi, Yasser; Berekovic, Mladen; Raghavan, Praveen (2017)