Browsing by author "Hershberg, Benjamin"
Now showing items 1-20 of 32
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A +70dBm IIP3 electrical-balance duplexer for highly-integrated tunable front-ends
van Liempd, Barend; Hershberg, Benjamin; Ariumi, Saneaki; Raczkowski, Kuba; Bink, Karl-Frederik; Karthaus, Udo; Martens, Ewout; Wambacq, Piet; Craninckx, Jan (2016) -
A +70dBm IIP3 single-ended electrical-balance duplexer in 0.18μm SOI CMOS
van Liempd, Barend; Hershberg, Benjamin; Raczkowski, Kuba; Ariumi, Saneaki; Karthaus, Udo; Bink, Karl-Frederik; Craninckx, Jan (2015) -
A 1-GS/s, 12-b, single-channel pipelined ADC with dead-zone-degenerated ring amplifiers
Lagos Benites, Jorge; Hershberg, Benjamin; Martens, Ewout; Wambacq, Piet; Craninckx, Jan (2019-03) -
A 1-MS/s to 1-GS/s Ringamp-Based Pipelined ADC With Fully Dynamic Reference Regulation and Stochastic Scope-on-Chip Background Monitoring in 16 nm
Hershberg, Benjamin; Markulic, Nereo; Lagos Benites, Jorge; Martens, Ewout; Dermit, Davide; Craninckx, Jan (2021) -
A 10.1 ENOB, 6.2fJ/con.-step, 500MS/s ringamp-based pipelined-SAR ADC with background calibration and dynamic reference regulation in 16nm CMOS
Lagos Benites, Jorge; Markulic, Nereo; Hershberg, Benjamin; Dermit, Davide; Shrivas, Mithlesh; Martens, Ewout; Craninckx, Jan (2021) -
A 10.1-ENOB, 6.2-fJ/conv.-step, 500-MS/s, Ringamp-Based Pipelined-SAR ADC With Background Calibration and Dynamic Reference Regulation in 16-nm CMOS
Lagos Benites, Jorge; Markulic, Nereo; Hershberg, Benjamin; Dermit, Davide; Shrivas, Mithlesh; Martens, Ewout; Craninckx, Jan (2022) -
A 16nm 69dB SNDR 300MSps ADC with capacitive reference stabilization
Martens, Ewout; Hershberg, Benjamin; Craninckx, Jan (2017) -
A 1Gsps, 12-bit, single-channel pipelined ADC with dead-zone-degenerated ring amplifiers
Lagos Benites, Jorge; Hershberg, Benjamin; Martens, Ewout; Wambacq, Piet; Craninckx, Jan (2018-04) -
A 1MS/s to 1GS/s Ringamp-Based Pipelined ADC with Fully Dynamic Reference Regulation and Stochastic Scope-on-Chip Background Monitoring in 16nm
Hershberg, Benjamin; Markulic, Nereo; Craninckx, Jan; Lagos Benites, Jorge; Martens, Ewout; Dermit, Davide (2020) -
A 3.2GS/s 10 ENOB 61mW ringamp ADC in 16nm with background monitoring of distortion
Hershberg, Benjamin; Martens, Ewout; van Liempd, Barend; Craninckx, Jan; Markulic, Nereo; Lagos Benites, Jorge; Dermit, Davide (2019) -
A 4-GS/s 10-ENOB 75-mW Ringamp ADC in 16-nm CMOS With Background Monitoring of Distortion
Hershberg, Benjamin; Dermit, Davide; van Liempd, Barend; Martens, Ewout; Markulic, Nereo; Lagos Benites, Jorge; Craninckx, Jan (2021) -
A 47.5MHz BW 4.7mW 67dB SNDR Ringamp Based Discrete-Time Delta Sigma ADC
Moura Santana, Lucas; Martens, Ewout; Lagos Benites, Jorge; Hershberg, Benjamin; Wambacq, Piet; Craninckx, Jan (2021) -
A 6-to-600MS/s fully dynamic ringamp pipelined ADC with asynchronous event-driven clocking in 16nm
Hershberg, Benjamin; van Liempd, Barend; Martens, Ewout; Craninckx, Jan; Markulic, Nereo; Dermit, Davide; Lagos Benites, Jorge (2019) -
A 69-dB SNDR 300-MS/s two-time interleaved pipelined SAR ADC in 16-nm CMOS FinFET with capacitive reference stabilization
Martens, Ewout; Hershberg, Benjamin; Craninckx, Jan (2018) -
A 9.1-12.7 GHz VCO in 28nm CMOS with a bottom-pinning bias technique for digital varactor stress reduction
Hershberg, Benjamin; Raczkowski, Kuba; Vaesen, Kristof; Craninckx, Jan (2014) -
A 9.2-12.7GHz wideband fractional-N subsampling PLL in 28nm CMOS with 280fs RMS jitter
Raczkowski, Kuba; Markulic, Nereo; Hershberg, Benjamin; Van Driessche, Joris; Craninckx, Jan (2014) -
A 9.2–12.7GHz wideband fractional-N subsampling PLL in 28nm CMOS with 280fs RMS jitter
Raczkowski, Kuba; Markulic, Nereo; Hershberg, Benjamin; Craninckx, Jan (2015) -
A 950 MHz Clock 47.5 MHz BW 4.7 mW 67 dB SNDR Discrete Time Delta Sigma ADC Leveraging Ring Amplification and Split-Source Comparator Based Quantizer in 28 nm CMOS
Moura Santana, Lucas; Martens, Ewout; Lagos Benites, Jorge; Hershberg, Benjamin; Wambacq, Piet; Craninckx, Jan (2022) -
A DTC-based subsampling PLL capable of self- calibrated fractional synthesis and two-point modulation
Markulic, Nereo; Raczkowski, Kuba; Martens, Ewout; Paro Filho, Pedro; Hershberg, Benjamin; Wambacq, Piet; Craninckx, Jan (2016) -
A dual-frequency 0.7-to-16GHz balance network for electrical balance duplexers
Hershberg, Benjamin; van Liempd, Barend; Zhang, Xiaoqiang; Wambacq, Piet; Craninckx, Jan (2016)