Browsing by author "Cleavelin, C.R."

Now showing items 1-2 of 2

A low-power multi-gate FET CMOS technology with 13.9ps inverter delay, large-scale integrated high performance digital circuits and SRAM

von Arnim, Klaus; Augendre, Emmanuel; Pacha, C.; Schulz, Thomas; San, Kemal Tamer; Bauer, F.; Nackaerts, Axel; Rooyackers, Rita; Vandeweyer, Tom; Degroote, Bart; Collaert, Nadine; Dixit, Abhisek; Singanamalla, Raghunath; Xiong, W.; Marshall, A.; Cleavelin, C.R.; Schrüfer, K.; Jurczak, Gosia (2007)
Layout options for stability tuning of SRAM cells in multi-gate=FET technologies

Bauer, F.; von Arnim, Klaus; Pacha, C.; Schultz, T.; Fulde, M.; Nackaerts, Axel; Jurczak, Gosia; Xiong, W.; San, K.T.; Cleavelin, C.R.; Schrüfer, K.; Georgakos, G.; Schmitt-Landsiedel, D. (2007)