Browsing by author "Lagos Benites, Jorge"
Now showing items 1-19 of 19
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A 1-GS/s, 12-b, single-channel pipelined ADC with dead-zone-degenerated ring amplifiers
Lagos Benites, Jorge; Hershberg, Benjamin; Martens, Ewout; Wambacq, Piet; Craninckx, Jan (2019-03) -
A 1-MS/s to 1-GS/s Ringamp-Based Pipelined ADC With Fully Dynamic Reference Regulation and Stochastic Scope-on-Chip Background Monitoring in 16 nm
Hershberg, Benjamin; Markulic, Nereo; Lagos Benites, Jorge; Martens, Ewout; Dermit, Davide; Craninckx, Jan (2021) -
A 1.67-GSps TI 10-Bit Ping-Pong SAR ADC With 51-dB SNDR in 16-nm FinFET
Dermit, Davide; Shrivas, Mithlesh; Bunsen, Keigo; Lagos Benites, Jorge; Craninckx, Jan; Martens, Ewout (2020) -
A 10.1 ENOB, 6.2fJ/con.-step, 500MS/s ringamp-based pipelined-SAR ADC with background calibration and dynamic reference regulation in 16nm CMOS
Lagos Benites, Jorge; Markulic, Nereo; Hershberg, Benjamin; Dermit, Davide; Shrivas, Mithlesh; Martens, Ewout; Craninckx, Jan (2021) -
A 10.1-ENOB, 6.2-fJ/conv.-step, 500-MS/s, Ringamp-Based Pipelined-SAR ADC With Background Calibration and Dynamic Reference Regulation in 16-nm CMOS
Lagos Benites, Jorge; Markulic, Nereo; Hershberg, Benjamin; Dermit, Davide; Shrivas, Mithlesh; Martens, Ewout; Craninckx, Jan (2022) -
A 1Gsps, 12-bit, single-channel pipelined ADC with dead-zone-degenerated ring amplifiers
Lagos Benites, Jorge; Hershberg, Benjamin; Martens, Ewout; Wambacq, Piet; Craninckx, Jan (2018-04) -
A 1MS/s to 1GS/s Ringamp-Based Pipelined ADC with Fully Dynamic Reference Regulation and Stochastic Scope-on-Chip Background Monitoring in 16nm
Hershberg, Benjamin; Markulic, Nereo; Craninckx, Jan; Lagos Benites, Jorge; Martens, Ewout; Dermit, Davide (2020) -
A 3.2GS/s 10 ENOB 61mW ringamp ADC in 16nm with background monitoring of distortion
Hershberg, Benjamin; Martens, Ewout; van Liempd, Barend; Craninckx, Jan; Markulic, Nereo; Lagos Benites, Jorge; Dermit, Davide (2019) -
A 3.3-GS/s 6-b Fully Dynamic Pipelined ADC With Linearized Dynamic Amplifier
Zheng, Zihao; Wei, Lai; Zhu, Yan; Chan, Chi-Hang; Martins, Rui P.; Lagos Benites, Jorge; Martens, Ewout; Craninckx, Jan (2022) -
A 4-GS/s 10-ENOB 75-mW Ringamp ADC in 16-nm CMOS With Background Monitoring of Distortion
Hershberg, Benjamin; Dermit, Davide; van Liempd, Barend; Martens, Ewout; Markulic, Nereo; Lagos Benites, Jorge; Craninckx, Jan (2021) -
A 47.5MHz BW 4.7mW 67dB SNDR Ringamp Based Discrete-Time Delta Sigma ADC
Moura Santana, Lucas; Martens, Ewout; Lagos Benites, Jorge; Hershberg, Benjamin; Wambacq, Piet; Craninckx, Jan (2021) -
A 6-to-600MS/s fully dynamic ringamp pipelined ADC with asynchronous event-driven clocking in 16nm
Hershberg, Benjamin; van Liempd, Barend; Martens, Ewout; Craninckx, Jan; Markulic, Nereo; Dermit, Davide; Lagos Benites, Jorge (2019) -
A 70MHz Bandwidth Time-Interleaved Noise-Shaping SAR Assisted Delta Sigma ADC with Digital Cross-Coupling in 28nm CMOS
Santana, Lucas Moura; Martens, Ewout; Lagos Benites, Jorge; Wambacq, Piet; Craninckx, Jan (2023) -
A 950 MHz Clock 47.5 MHz BW 4.7 mW 67 dB SNDR Discrete Time Delta Sigma ADC Leveraging Ring Amplification and Split-Source Comparator Based Quantizer in 28 nm CMOS
Moura Santana, Lucas; Martens, Ewout; Lagos Benites, Jorge; Hershberg, Benjamin; Wambacq, Piet; Craninckx, Jan (2022) -
A single-channel 5.5mW 3.3GS/s 6b fully dynamic pipelined ADC with post-amplification residue generation
Zheng, Zihao; Wei, Lai; Lagos Benites, Jorge; Martens, Ewout; Zhu, Yan; Chan, Chi-Hang; Craninckx, Jan; Martins, Rui P. (2020-02) -
A Single-Channel, 600-MS/s, 12-b, ringamp-based pipelined ADC in 28-nm CMOS
Lagos Benites, Jorge; Hershberg, Benjamin; Martens, Ewout; Wambacq, Piet; Craninckx, Jan (2019-02) -
A single-channel, 600Msps, 12bit, Ringamp-based pipelined ADC in 28nm
Lagos Benites, Jorge; Hershberg, Benjamin; Martens, Ewout; Wambacq, Piet; Craninckx, Jan (2017) -
An auxiliary-channel-sharing background distortion and gain calibration achieving >8dB SFDR improvement over 4th Nyquist zone in 1GS/s ADC
Wei, Lai; Zheng, Zihao; Markulic, Nereo; Lagos Benites, Jorge; Martens, Ewout; Zhu, Yan; Chan, Chi-Hang; Craninckx, Jan; Martins, Rui Paulo (2021) -
Asynchronous Event-Driven Clocking and Control in Pipelined ADCs
Hershberg, Benjamin; van Liempd, Barend; Markulic, Nereo; Lagos Benites, Jorge; Martens, Ewout; Dermit, Davide; Craninckx, Jan (2021)