Browsing by author "Craninckx, Jan"
Now showing items 1-20 of 224
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4G terminals: how are we going to design them ?
Craninckx, Jan; Donnay, Stephane (2003-06) -
A +70dBm IIP3 electrical-balance duplexer for highly-integrated tunable front-ends
van Liempd, Barend; Hershberg, Benjamin; Ariumi, Saneaki; Raczkowski, Kuba; Bink, Karl-Frederik; Karthaus, Udo; Martens, Ewout; Wambacq, Piet; Craninckx, Jan (2016) -
A +70dBm IIP3 single-ended electrical-balance duplexer in 0.18μm SOI CMOS
van Liempd, Barend; Hershberg, Benjamin; Raczkowski, Kuba; Ariumi, Saneaki; Karthaus, Udo; Bink, Karl-Frederik; Craninckx, Jan (2015) -
A 0.045mm² 0.1-6GHz reconfigurable multi-band, multi-gain LNA for SDR
Geis, Arnd; Rolain, Yves; Vandersteen, Gerd; Craninckx, Jan (2010) -
A 0.1-5GHz dual-VCO software-defined sigma delta frequency synthesizer in 45nm digital CMOS
Nuzzo, Pierluigi; Vengattaramane, Kameswaran; Ingels, Mark; Giannini, Vito; Steyaert, Michiel; Craninckx, Jan (2009) -
A 0.22mm2 CMOS resistive charge-based direct-launch digital transmitter with -159dBc/Hz out of band noise
Paro Filho, Pedro; Ingels, Mark; Wambacq, Piet; Craninckx, Jan (2016) -
A 0.5mm² power-scalable 0.5-3.8GHz CMOS DT-SDR receiver with 2nd order RF band-pass sampler
Geis, Arnd; Ryckaert, Julien; Bos, Lynn; Vandersteen, Gerd; Rolain, Yves; Craninckx, Jan (2010) -
A 0.65-to-1.4 nJ/burst 3-to-10 GHz UWB all-digital TX in 90 nm CMOS for IEEE 802.15.4a
Ryckaert, Julien; Van der Plas, Geert; De Heyn, Vincent; Desset, Claude; Van Poucke, Bart; Craninckx, Jan (2007) -
A 0.65-to-1.4nJ/burst 3-to-10GHz UWB digital transmitter in 90nm CMOS for IEEE 802.15.4a
Ryckaert, Julien; Van der Plas, Geert; De Heyn, Vincent; Desset, Claude; Vanwijnsberghe, Geert; Van Poucke, Bart; Craninckx, Jan (2007-02) -
A 0.7 - 1GHz tunable RF front-end module for FDD and in-band full-duplex using SOI CMOS and SAW resonators
van Liempd, Barend; Visweswaran, Akshay; Hitomi, Shinya; Ariumi, Saneaki; Wambacq, Piet; Craninckx, Jan (2017) -
A 0.7 to 1 GHz switched-LC N-path LNA resilient to FDD-LTE self-interference at $440 MHz offset
Qi, Gengzhen; van Liempd, Barend; Mak, Pui-In; Martins, Rui P.; Craninckx, Jan (2017) -
A 0.7-1.15GHz complementary common-gate LNA in 0.18μm SOl CMOS with +15dBm IIP3 and >1kV HBM ESD protection
van Liempd, Barend; Ariumi, Saneaki; Martens, Ewout; Chen, Shih-Hung; Wambacq, Piet; Craninckx, Jan (2015) -
A 0.9V 0.4-6GHz harmonic recombination SDR receiver in 28nm CMOS with HR3/HR5 and IIP2 calibration
van Liempd, Barend; Borremans, Jonathan; Martens, Ewout; Cha, Sungwoo; Suys, Hans; Verbruggen, Bob; Craninckx, Jan (2014) -
A 0.9V low-power 0.4-6GHz linear SDR receiver in 28nm CMOS
Borremans, Jonathan; van Liempd, Barend; Martens, Ewout; Cha, Sungwoo; Craninckx, Jan (2013) -
A 1-GS/s, 12-b, single-channel pipelined ADC with dead-zone-degenerated ring amplifiers
Lagos Benites, Jorge; Hershberg, Benjamin; Martens, Ewout; Wambacq, Piet; Craninckx, Jan (2019-03) -
A 1-MS/s to 1-GS/s Ringamp-Based Pipelined ADC With Fully Dynamic Reference Regulation and Stochastic Scope-on-Chip Background Monitoring in 16 nm
Hershberg, Benjamin; Markulic, Nereo; Lagos Benites, Jorge; Martens, Ewout; Dermit, Davide; Craninckx, Jan (2021) -
A 1.67-GSps TI 10-Bit Ping-Pong SAR ADC With 51-dB SNDR in 16-nm FinFET
Dermit, Davide; Shrivas, Mithlesh; Bunsen, Keigo; Lagos Benites, Jorge; Craninckx, Jan; Martens, Ewout (2020) -
A 1.7mW 11b 250MS/s 2-times interleaved fully dynamic pipelined SAR ADC in 40nm digital CMOS
Verbruggen, Bob; Iriguchi, Masao; Craninckx, Jan (2012) -
A 10-bit, 550-fs step digital-to-time converter in 28nm CMOS
Markulic, Nereo; Raczkowski, Kuba; Wambacq, Piet; Craninckx, Jan (2014) -
A 10.1 ENOB, 6.2fJ/con.-step, 500MS/s ringamp-based pipelined-SAR ADC with background calibration and dynamic reference regulation in 16nm CMOS
Lagos Benites, Jorge; Markulic, Nereo; Hershberg, Benjamin; Dermit, Davide; Shrivas, Mithlesh; Martens, Ewout; Craninckx, Jan (2021)