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Energy efficient memory architecture for high speed decoding of block turbo-codes with the Fang-Buda algorithm

dc.contributor.authorBougard, Bruno
dc.contributor.authorRullmann, Markus
dc.contributor.authorBrockmeyer, Erik
dc.contributor.authorVan der Perre, Liesbet
dc.contributor.authorCatthoor, Francky
dc.contributor.authorDehaene, Wim
dc.date.accessioned2021-10-16T00:48:49Z
dc.date.available2021-10-16T00:48:49Z
dc.date.issued2005-01
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/10134
dc.sourceIIOimport
dc.titleEnergy efficient memory architecture for high speed decoding of block turbo-codes with the Fang-Buda algorithm
dc.typeJournal article
dc.contributor.imecauthorCatthoor, Francky
dc.contributor.imecauthorDehaene, Wim
dc.contributor.orcidimecCatthoor, Francky::0000-0002-3599-8515
dc.source.peerreviewno
dc.source.beginpage79
dc.source.endpage92
dc.source.journalJournal of VLSI Signal Processing
dc.source.issue1_2
dc.source.volume39
imec.availabilityPublished - imec


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