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A new scalable self-aligned dual-bit split-gate charge trapping memory device

dc.contributor.authorBreuil, Laurent
dc.contributor.authorHaspeslagh, Luc
dc.contributor.authorBlomme, Pieter
dc.contributor.authorWellekens, Dirk
dc.contributor.authorDe Vos, Joeri
dc.contributor.authorLorenzini, Martino
dc.contributor.authorVan Houdt, Jan
dc.date.accessioned2021-10-16T00:50:13Z
dc.date.available2021-10-16T00:50:13Z
dc.date.issued2005
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/10151
dc.sourceIIOimport
dc.titleA new scalable self-aligned dual-bit split-gate charge trapping memory device
dc.typeJournal article
dc.contributor.imecauthorBreuil, Laurent
dc.contributor.imecauthorHaspeslagh, Luc
dc.contributor.imecauthorBlomme, Pieter
dc.contributor.imecauthorWellekens, Dirk
dc.contributor.imecauthorDe Vos, Joeri
dc.contributor.imecauthorVan Houdt, Jan
dc.contributor.orcidimecBreuil, Laurent::0000-0003-2869-1651
dc.contributor.orcidimecDe Vos, Joeri::0000-0002-9332-9336
dc.contributor.orcidimecVan Houdt, Jan::0000-0003-1381-6925
dc.source.peerreviewno
dc.source.beginpage2250
dc.source.endpage2257
dc.source.journalIEEE Trans. Electron Devices
dc.source.issue10
dc.source.volume52
imec.availabilityPublished - imec


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