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Analysis of the parasitic S/D resistance in multiple-gate FETs

dc.contributor.authorDixit, Abhisek
dc.contributor.authorKottantharayil, Anil
dc.contributor.authorCollaert, Nadine
dc.contributor.authorGoodwin, Michael
dc.contributor.authorJurczak, Gosia
dc.contributor.authorDe Meyer, Kristin
dc.date.accessioned2021-10-16T01:23:41Z
dc.date.available2021-10-16T01:23:41Z
dc.date.issued2005
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/10395
dc.sourceIIOimport
dc.titleAnalysis of the parasitic S/D resistance in multiple-gate FETs
dc.typeJournal article
dc.contributor.imecauthorCollaert, Nadine
dc.contributor.imecauthorJurczak, Gosia
dc.contributor.imecauthorDe Meyer, Kristin
dc.contributor.orcidimecCollaert, Nadine::0000-0002-8062-3165
dc.source.peerreviewno
dc.source.beginpage1132
dc.source.endpage1140
dc.source.journalIEEE Trans. Electron Devices
dc.source.issue6
dc.source.volume52
imec.availabilityPublished - imec


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