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Test circuits for fast and reliable assessment if CDM robustness of I/O stages

dc.contributor.authorStadler, W.
dc.contributor.authorEsmark, K.
dc.contributor.authorReynders, K.
dc.contributor.authorZubeidat, M.
dc.contributor.authorGraf, M.
dc.contributor.authorWilkening, W.
dc.contributor.authorWillemen, J.
dc.contributor.authorQu, D.
dc.contributor.authorMettler, S.
dc.contributor.authorEtherton, M.
dc.contributor.authorNuernbergk, D.
dc.contributor.authorWolf, H.
dc.contributor.authorGieser, H.
dc.contributor.authorSoppa, W.
dc.contributor.authorDe Heyn, Vincent
dc.contributor.authorMahadeva Iyer, Natarajan
dc.contributor.authorGroeseneken, Guido
dc.contributor.authorMorena, E.
dc.contributor.authorStella, I.
dc.contributor.authorAndreini, A.
dc.contributor.authorLitzenberger, M.
dc.contributor.authorPogany, D.
dc.contributor.authorGornik, E.
dc.contributor.authorFoss, C.
dc.contributor.authorKonrad, A.
dc.contributor.authorFrank, M.
dc.date.accessioned2021-10-16T05:24:05Z
dc.date.available2021-10-16T05:24:05Z
dc.date.issued2005
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/11266
dc.sourceIIOimport
dc.titleTest circuits for fast and reliable assessment if CDM robustness of I/O stages
dc.typeJournal article
dc.contributor.imecauthorDe Heyn, Vincent
dc.contributor.imecauthorGroeseneken, Guido
dc.source.peerreviewno
dc.source.beginpage269
dc.source.endpage277
dc.source.journalMicroelectronics Reliability
dc.source.issue2
dc.source.volume45
imec.availabilityPublished - imec


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