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Variable tapered pareto buffer design and implementation allowing run-time configuration for low power embedded SRAMs

dc.contributor.authorWang, Hua
dc.contributor.authorMiranda, Miguel
dc.contributor.authorPapanikolaou, Antonis
dc.contributor.authorCatthoor, Francky
dc.contributor.authorDehaene, Wim
dc.date.accessioned2021-10-16T07:01:32Z
dc.date.available2021-10-16T07:01:32Z
dc.date.issued2005-10
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/11539
dc.sourceIIOimport
dc.titleVariable tapered pareto buffer design and implementation allowing run-time configuration for low power embedded SRAMs
dc.typeJournal article
dc.contributor.imecauthorCatthoor, Francky
dc.contributor.imecauthorDehaene, Wim
dc.contributor.orcidimecCatthoor, Francky::0000-0002-3599-8515
dc.source.peerreviewno
dc.source.beginpage1127
dc.source.endpage1135
dc.source.journalIEEE Trans. VLSI Systems
dc.source.issue10
dc.source.volume13
imec.availabilityPublished - imec


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