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Reduction of the anomalous VT behavior in MOSFETs with High-k/metal gate stacks

dc.contributor.authorFerain, Isabelle
dc.contributor.authorPantisano, Luigi
dc.contributor.authorKottantharayil, Anil
dc.contributor.authorPetry, Jasmine
dc.contributor.authorTrojman, Lionel
dc.contributor.authorCollaert, Nadine
dc.contributor.authorJurczak, Gosia
dc.contributor.authorDe Meyer, Kristin
dc.date.accessioned2021-10-16T16:06:43Z
dc.date.available2021-10-16T16:06:43Z
dc.date.issued2007
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/12151
dc.sourceIIOimport
dc.titleReduction of the anomalous VT behavior in MOSFETs with High-k/metal gate stacks
dc.typeJournal article
dc.contributor.imecauthorCollaert, Nadine
dc.contributor.imecauthorJurczak, Gosia
dc.contributor.imecauthorDe Meyer, Kristin
dc.contributor.orcidimecCollaert, Nadine::0000-0002-8062-3165
dc.source.peerreviewno
dc.source.beginpage1882
dc.source.endpage1885
dc.source.journalMicroelectronic Engineering
dc.source.issue9_10
dc.source.volume84
imec.availabilityPublished - imec
imec.internalnotesPaper from INFOS 2007


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