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dc.contributor.authorRudenko, Tamara
dc.contributor.authorKilchytska, Valeria
dc.contributor.authorCollaert, Nadine
dc.contributor.authorJurczak, Gosia
dc.contributor.authorNazarov, A.
dc.contributor.authorFlandre, Denis
dc.date.accessioned2021-10-16T19:15:16Z
dc.date.available2021-10-16T19:15:16Z
dc.date.issued2007
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/12817
dc.sourceIIOimport
dc.titleReduction of gate-to-channel tunnelling current in FinFET structures
dc.typeJournal article
dc.contributor.imecauthorCollaert, Nadine
dc.contributor.imecauthorJurczak, Gosia
dc.contributor.orcidimecCollaert, Nadine::0000-0002-8062-3165
dc.source.peerreviewno
dc.source.beginpage1466
dc.source.endpage1473
dc.source.journalSolid-State Electronics
dc.source.issue11_12
dc.source.volume51
imec.availabilityPublished - imec


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