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Substrate bias effect linked to parasitic series resistance in multiple-gate SOI MOSFETs

dc.contributor.authorRudenko, Tamara
dc.contributor.authorKilchytska, Valeria
dc.contributor.authorCollaert, Nadine
dc.contributor.authorJurczak, Gosia
dc.contributor.authorNazarov, Alexey
dc.contributor.authorFlandre, Denis
dc.date.accessioned2021-10-16T19:15:37Z
dc.date.available2021-10-16T19:15:37Z
dc.date.issued2007-09
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/12818
dc.sourceIIOimport
dc.titleSubstrate bias effect linked to parasitic series resistance in multiple-gate SOI MOSFETs
dc.typeJournal article
dc.contributor.imecauthorCollaert, Nadine
dc.contributor.imecauthorJurczak, Gosia
dc.contributor.orcidimecCollaert, Nadine::0000-0002-8062-3165
dc.date.embargo9999-12-31
dc.source.peerreviewno
dc.source.beginpage834
dc.source.endpage836
dc.source.journalIEEE Electron Device Letters
dc.source.issue9
dc.source.volume28
imec.availabilityPublished - open access


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