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The potential of double patterning immersion lithography for the 32nm half pitch node

dc.contributor.authorWiaux, Vincent
dc.contributor.authorStorms, Greet
dc.contributor.authorCheng, Shaunee
dc.contributor.authorMaenhoudt, Mireille
dc.date.accessioned2021-10-16T21:43:43Z
dc.date.available2021-10-16T21:43:43Z
dc.date.issued2007-08
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/13225
dc.sourceIIOimport
dc.titleThe potential of double patterning immersion lithography for the 32nm half pitch node
dc.typeJournal article
dc.contributor.imecauthorWiaux, Vincent
dc.source.peerreviewno
dc.source.beginpage19
dc.source.endpage22
dc.source.journalEuroAsia Semiconductor
dc.identifier.urlhttp://www.euroasiasemiconductor.com/print.php?id=8451
imec.availabilityPublished - imec


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