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Influence of extreme thinning on 130nm CMOS devices for 3D integration

dc.contributor.authorDe Munck, Koen
dc.contributor.authorChiarella, Thomas
dc.contributor.authorDe Moor, Piet
dc.contributor.authorSwinnen, Bart
dc.contributor.authorVan Hoof, Chris
dc.date.accessioned2021-10-17T06:46:20Z
dc.date.available2021-10-17T06:46:20Z
dc.date.issued2008
dc.identifier.issn0741-3106
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/13615
dc.sourceIIOimport
dc.titleInfluence of extreme thinning on 130nm CMOS devices for 3D integration
dc.typeJournal article
dc.contributor.imecauthorDe Munck, Koen
dc.contributor.imecauthorChiarella, Thomas
dc.contributor.imecauthorDe Moor, Piet
dc.contributor.imecauthorSwinnen, Bart
dc.contributor.imecauthorVan Hoof, Chris
dc.contributor.orcidimecChiarella, Thomas::0000-0002-6155-9030
dc.date.embargo9999-12-31
dc.source.peerreviewyes
dc.source.beginpage322
dc.source.endpage324
dc.source.journalIEEE Electron Device Letters
dc.source.issue4
dc.source.volume29
imec.availabilityPublished - open access


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