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Gate influence on the layout sensitivity of Si1-xGex S/D and Si1-yCy S/D transistors, including an analytical model

dc.contributor.authorEneman, Geert
dc.contributor.authorSimoen, Eddy
dc.contributor.authorVerheyen, Peter
dc.contributor.authorDe Meyer, Kristin
dc.date.accessioned2021-10-17T07:00:12Z
dc.date.available2021-10-17T07:00:12Z
dc.date.issued2008
dc.identifier.issn0018-9383
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/13693
dc.sourceIIOimport
dc.titleGate influence on the layout sensitivity of Si1-xGex S/D and Si1-yCy S/D transistors, including an analytical model
dc.typeJournal article
dc.contributor.imecauthorEneman, Geert
dc.contributor.imecauthorSimoen, Eddy
dc.contributor.imecauthorVerheyen, Peter
dc.contributor.imecauthorDe Meyer, Kristin
dc.contributor.orcidimecEneman, Geert::0000-0002-5849-3384
dc.contributor.orcidimecSimoen, Eddy::0000-0002-5218-4046
dc.date.embargo9999-12-31
dc.source.peerreviewyes
dc.source.beginpage2703
dc.source.endpage2711
dc.source.journalIEEE Transactions on Electron Devices
dc.source.issue10
dc.source.volume55
imec.availabilityPublished - open access


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