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Investigation of high-k-metal gate integration for sub 45 nm planar bulk CMOS technologies

dc.contributor.authorSinganamalla, Raghunath
dc.date.accessioned2021-10-17T10:49:58Z
dc.date.available2021-10-17T10:49:58Z
dc.date.issued2008-12
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/14483
dc.sourceIIOimport
dc.titleInvestigation of high-k-metal gate integration for sub 45 nm planar bulk CMOS technologies
dc.typePHD thesis
dc.date.embargo9999-12-31
dc.source.peerreviewno
dc.contributor.thesisadvisorDe Meyer, Kristin
imec.availabilityPublished - open access


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