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The reliability margin of interconnects for advanced memory technologies

dc.contributor.authorBeyer, Gerald
dc.contributor.authorDemuynck, Steven
dc.contributor.authorStucchi, Michele
dc.contributor.authorTokei, Zsolt
dc.date.accessioned2021-10-17T21:22:50Z
dc.date.available2021-10-17T21:22:50Z
dc.date.issued2009
dc.identifier.issn0038-111X
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/14985
dc.sourceIIOimport
dc.titleThe reliability margin of interconnects for advanced memory technologies
dc.typeJournal article
dc.contributor.imecauthorBeyer, Gerald
dc.contributor.imecauthorDemuynck, Steven
dc.contributor.imecauthorStucchi, Michele
dc.contributor.imecauthorTokei, Zsolt
dc.source.peerreviewno
dc.source.beginpage14
dc.source.endpage27
dc.source.journalSolid State Technology
dc.source.issue5
dc.source.volume52
dc.identifier.urlhttp://www.electroiq.com/index/display/semiconductors-article-display/360523/articles/solid-state-technology/volume-52/issue-5/f
imec.availabilityPublished - imec


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