Multiple-valued reversible logic circuits
| dc.contributor.author | De Vos, Alexis | |
| dc.contributor.author | Van Rentergem, Yvan | |
| dc.date.accessioned | 2021-10-17T21:49:28Z | |
| dc.date.available | 2021-10-17T21:49:28Z | |
| dc.date.issued | 2009 | |
| dc.identifier.issn | 1542-3980 | |
| dc.identifier.uri | https://imec-publications.be/handle/20.500.12860/15187 | |
| dc.source | IIOimport | |
| dc.title | Multiple-valued reversible logic circuits | |
| dc.type | Journal article | |
| dc.date.embargo | 9999-12-31 | |
| dc.source.peerreview | yes | |
| dc.source.beginpage | 489 | |
| dc.source.endpage | 505 | |
| dc.source.journal | Journal of Multiple-Valued Logic and Soft Computing | |
| dc.source.volume | 15 | |
| imec.availability | Published - open access |