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Reconfigurable AGU: an address generation unit based on address calculation pattern for low energy and high performance embedded processors

dc.contributor.authorTaniguchi, Ittetsu
dc.contributor.authorRaghavan, Praveen
dc.contributor.authorJayapala, Murali
dc.contributor.authorCatthoor, Francky
dc.contributor.authorTakeuchi, Yoshinori
dc.contributor.authorImai, Mahasaru
dc.date.accessioned2021-10-18T03:30:40Z
dc.date.available2021-10-18T03:30:40Z
dc.date.issued2009
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/16291
dc.sourceIIOimport
dc.titleReconfigurable AGU: an address generation unit based on address calculation pattern for low energy and high performance embedded processors
dc.typeJournal article
dc.contributor.imecauthorJayapala, Murali
dc.contributor.imecauthorCatthoor, Francky
dc.contributor.orcidimecJayapala, Murali::0000-0001-7917-0149
dc.contributor.orcidimecCatthoor, Francky::0000-0002-3599-8515
dc.source.peerreviewno
dc.source.beginpage1161
dc.source.endpage1173
dc.source.journalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
dc.source.issue4
dc.source.volumeE92-A
imec.availabilityPublished - imec


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