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A 2.6 mW 6 bit 2.2 GS/s fully dynamic pipeline ADC in 40 nm Digital CMOS

dc.contributor.authorVerbruggen, Bob
dc.contributor.authorCraninckx, Jan
dc.contributor.authorKuijk, Maarten
dc.contributor.authorWambacq, Piet
dc.contributor.authorVan der Plas, Geert
dc.date.accessioned2021-10-18T23:40:46Z
dc.date.available2021-10-18T23:40:46Z
dc.date.issued2010
dc.identifier.issn0018-9200
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/18259
dc.sourceIIOimport
dc.titleA 2.6 mW 6 bit 2.2 GS/s fully dynamic pipeline ADC in 40 nm Digital CMOS
dc.typeJournal article
dc.contributor.imecauthorCraninckx, Jan
dc.contributor.imecauthorWambacq, Piet
dc.contributor.imecauthorVan der Plas, Geert
dc.contributor.orcidimecCraninckx, Jan::0000-0002-3980-0203
dc.contributor.orcidimecWambacq, Piet::0000-0003-4388-7257
dc.contributor.orcidimecVan der Plas, Geert::0000-0002-4975-6672
dc.date.embargo9999-12-31
dc.source.peerreviewyes
dc.source.beginpage2080
dc.source.endpage2090
dc.source.journalIEEE Journal of Solid-State Circuits
dc.source.issue10
dc.source.volume45
imec.availabilityPublished - open access


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