Process characterization and reliability issues of three dimension-stacked integrated circuit (3D-SIC) structures
dc.contributor.author | Yang, Yu | |
dc.date.accessioned | 2021-10-19T00:41:12Z | |
dc.date.available | 2021-10-19T00:41:12Z | |
dc.date.issued | 2010-11 | |
dc.identifier.uri | https://imec-publications.be/handle/20.500.12860/18380 | |
dc.source | IIOimport | |
dc.title | Process characterization and reliability issues of three dimension-stacked integrated circuit (3D-SIC) structures | |
dc.type | PHD thesis | |
dc.date.embargo | 9999-12-31 | |
dc.source.peerreview | no | |
dc.contributor.thesisadvisor | Verlinden, Albert | |
dc.contributor.thesisadvisor | Van Hoof, Chris | |
imec.availability | Published - open access |