Definition of dielectric breakdown for ultra thin (<2nm) gate oxides

dc.contributor.author	Depas, Michel
dc.contributor.author	Nigam, Tanya
dc.contributor.author	Heyns, Marc
dc.date.accessioned	2021-09-30T08:12:02Z
dc.date.available	2021-09-30T08:12:02Z
dc.date.issued	1997
dc.identifier.uri	https://imec-publications.be/handle/20.500.12860/1854
dc.source	IIOimport
dc.title	Definition of dielectric breakdown for ultra thin (<2nm) gate oxides
dc.type	Journal article
dc.contributor.imecauthor	Heyns, Marc
dc.date.embargo	9999-12-31
dc.source.peerreview	no
dc.source.beginpage	725
dc.source.endpage	728
dc.source.journal	Solid-State Electronics
dc.source.issue	5
dc.source.volume	41
imec.availability	Published - open access