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Test-architecture optimization and test scheduling for TSV-based 3D stacked ICs

dc.contributor.authorNoia, Brandon
dc.contributor.authorChakrabarty, Krishnendu
dc.contributor.authorGoel, Sandeep K.
dc.contributor.authorMarinissen, Erik Jan
dc.contributor.authorVerbree, Jouke
dc.date.accessioned2021-10-19T16:45:29Z
dc.date.available2021-10-19T16:45:29Z
dc.date.issued2011-11
dc.identifier.issn0278-0070
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/19490
dc.sourceIIOimport
dc.titleTest-architecture optimization and test scheduling for TSV-based 3D stacked ICs
dc.typeJournal article
dc.contributor.imecauthorMarinissen, Erik Jan
dc.contributor.orcidimecMarinissen, Erik Jan::0000-0002-5058-8303
dc.source.peerreviewyes
dc.source.beginpage1705
dc.source.endpage1718
dc.source.journalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
dc.source.issue11
dc.source.volume30
dc.identifier.urlhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6046180
imec.availabilityPublished - imec


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