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A 4.4 pJ/access 80 MHz, 128 kbit variability resilient SRAM with multi-sized sense amplifier redundancy

dc.contributor.authorSharma, Vibhu
dc.contributor.authorCosemans, Stefan
dc.contributor.authorAshouei, Maryam
dc.contributor.authorHuisken, Jos
dc.contributor.authorCatthoor, Francky
dc.contributor.authorDehaene, Wim
dc.date.accessioned2021-10-19T18:41:41Z
dc.date.available2021-10-19T18:41:41Z
dc.date.issued2011
dc.identifier.issn0018-9200
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/19764
dc.sourceIIOimport
dc.titleA 4.4 pJ/access 80 MHz, 128 kbit variability resilient SRAM with multi-sized sense amplifier redundancy
dc.typeJournal article
dc.contributor.imecauthorCosemans, Stefan
dc.contributor.imecauthorCatthoor, Francky
dc.contributor.imecauthorDehaene, Wim
dc.contributor.orcidimecCatthoor, Francky::0000-0002-3599-8515
dc.date.embargo9999-12-31
dc.source.peerreviewyes
dc.source.beginpage2416
dc.source.endpage2430
dc.source.journalIEEE Journal of Solid-State Circuits
dc.source.issue10
dc.source.volume46
dc.identifier.urlhttp://dx.doi.org/10.1109/JSSC.2011.2159056
imec.availabilityPublished - open access


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