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4+1-transistor pixel architecture for high-speed, high-resolution CMOS image sensors

dc.contributor.authorXhakoni, Adi
dc.contributor.authorSan Segundo Bello, David
dc.contributor.authorDe Wit, Pieter
dc.contributor.authorGielen, Georges
dc.date.accessioned2021-10-19T21:54:52Z
dc.date.available2021-10-19T21:54:52Z
dc.date.issued2011
dc.identifier.issn0013-5194
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/20160
dc.sourceIIOimport
dc.title4+1-transistor pixel architecture for high-speed, high-resolution CMOS image sensors
dc.typeJournal article
dc.contributor.imecauthorGielen, Georges
dc.source.peerreviewyes
dc.source.beginpage1221
dc.source.endpage1223
dc.source.journalElectronics Letters
dc.source.issue22
dc.source.volume47
imec.availabilityPublished - imec


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