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Lessons learned from 3D DRAM-on-logic chip development

dc.contributor.authorBeyne, Eric
dc.date.accessioned2021-10-20T10:05:53Z
dc.date.available2021-10-20T10:05:53Z
dc.date.issued2012-02
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/20359
dc.sourceIIOimport
dc.titleLessons learned from 3D DRAM-on-logic chip development
dc.typeJournal article
dc.contributor.imecauthorBeyne, Eric
dc.contributor.orcidimecBeyne, Eric::0000-0002-3096-050X
dc.date.embargo9999-12-31
dc.source.peerreviewno
dc.source.journalSemiconductor Packaging News
dc.identifier.urlhttp://www.semiconductorpackagingnews.com/articles/article_34910.shtml
imec.availabilityPublished - open access


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