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Synthesis of pipelined DSP accelerators with dynamic scheduling

dc.contributor.authorSchaumont, Patrick
dc.contributor.authorVanthournout, Bart
dc.contributor.authorBolsens, Ivo
dc.contributor.authorDe Man, Hugo
dc.date.accessioned2021-09-30T09:28:36Z
dc.date.available2021-09-30T09:28:36Z
dc.date.issued1997
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/2116
dc.sourceIIOimport
dc.titleSynthesis of pipelined DSP accelerators with dynamic scheduling
dc.typeJournal article
dc.contributor.imecauthorDe Man, Hugo
dc.date.embargo9999-12-31
dc.source.peerreviewno
dc.source.beginpage59
dc.source.endpage68
dc.source.journalIEEE Trans. Very Large Scale Integration (VLSI) Systems
dc.source.issue1
dc.source.volume5
imec.availabilityPublished - open access


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