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Impact of process and geometrical parameters on the electrical characteristics of vertical nanowire silicon n-TFETs

dc.contributor.authorVandooren, Anne
dc.contributor.authorLeonelli, Daniele
dc.contributor.authorRooyackers, Rita
dc.contributor.authorArstila, Kai
dc.contributor.authorGroeseneken, Guido
dc.contributor.authorHuyghebaert, Cedric
dc.date.accessioned2021-10-20T18:04:16Z
dc.date.available2021-10-20T18:04:16Z
dc.date.issued2012
dc.identifier.issn0038-1101
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/21746
dc.sourceIIOimport
dc.titleImpact of process and geometrical parameters on the electrical characteristics of vertical nanowire silicon n-TFETs
dc.typeJournal article
dc.contributor.imecauthorVandooren, Anne
dc.contributor.imecauthorLeonelli, Daniele
dc.contributor.imecauthorGroeseneken, Guido
dc.contributor.imecauthorHuyghebaert, Cedric
dc.contributor.orcidimecVandooren, Anne::0000-0002-2412-0176
dc.contributor.orcidimecHuyghebaert, Cedric::0000-0001-6043-7130
dc.source.peerreviewyes
dc.source.beginpage82
dc.source.endpage87
dc.source.journalSolid-State Electronics
dc.source.volume72
imec.availabilityPublished - imec


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