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A 1.7mW 11b 250MS/s 2-times interleaved fully dynamic pipelined SAR ADC in 40nm digital CMOS

dc.contributor.authorVerbruggen, Bob
dc.contributor.authorIriguchi, Masao
dc.contributor.authorCraninckx, Jan
dc.date.accessioned2021-10-20T18:17:29Z
dc.date.available2021-10-20T18:17:29Z
dc.date.issued2012
dc.identifier.issn0018-9200
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/21770
dc.sourceIIOimport
dc.titleA 1.7mW 11b 250MS/s 2-times interleaved fully dynamic pipelined SAR ADC in 40nm digital CMOS
dc.typeJournal article
dc.contributor.imecauthorCraninckx, Jan
dc.contributor.orcidimecCraninckx, Jan::0000-0002-3980-0203
dc.date.embargo9999-12-31
dc.source.peerreviewyes
dc.source.beginpage2880
dc.source.endpage2887
dc.source.journalIEEE Journal of Solid-State Circuits
dc.source.issue12
dc.source.volume47
imec.availabilityPublished - open access


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