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Dry etching patterning requirements for multi-gate devices

dc.contributor.authorAltamirano Sanchez, Efrain
dc.contributor.authorVandeweyer, Tom
dc.contributor.authorDemand, Marc
dc.contributor.authorBoullart, Werner
dc.date.accessioned2021-10-21T06:42:24Z
dc.date.available2021-10-21T06:42:24Z
dc.date.issued2013-09
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/21968
dc.sourceIIOimport
dc.titleDry etching patterning requirements for multi-gate devices
dc.typeBook chapter
dc.contributor.imecauthorAltamirano Sanchez, Efrain
dc.contributor.imecauthorVandeweyer, Tom
dc.contributor.imecauthorDemand, Marc
dc.contributor.imecauthorBoullart, Werner
dc.contributor.orcidimecBoullart, Werner::0000-0001-7614-2097
dc.source.peerreviewno
dc.source.beginpage29
dc.source.bookCMOS Nanoelectronics: Innovative Devices, Architectures, and Applications
dc.source.endpage50
dc.identifier.urlhttp://www.panstanford.com/books/9789814364027.html#toc
imec.availabilityPublished - imec
imec.internalnotesChapter 2


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