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Design space exploration of distributed loop buffer architectures with incompatible loop-nest organisation in embedded systems

dc.contributor.authorArtes, Antonio
dc.contributor.authorFasthuber, Robert
dc.contributor.authorAyala, Jose
dc.contributor.authorRaghavan, Praveen
dc.contributor.authorCatthoor, Francky
dc.date.accessioned2021-10-21T06:43:08Z
dc.date.available2021-10-21T06:43:08Z
dc.date.issued2013
dc.identifier.issn1939-8018
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/21990
dc.sourceIIOimport
dc.titleDesign space exploration of distributed loop buffer architectures with incompatible loop-nest organisation in embedded systems
dc.typeJournal article
dc.contributor.imecauthorCatthoor, Francky
dc.contributor.orcidimecCatthoor, Francky::0000-0002-3599-8515
dc.source.peerreviewyes
dc.source.beginpage69
dc.source.endpage85
dc.source.journalJournal of Signal Processing Systems
dc.source.volume72
imec.availabilityPublished - imec


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