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Use of SSTA tools for evaluating BTI impact on combinational circuits

dc.contributor.authorCamargo, V. V. A.
dc.contributor.authorKaczer, Ben
dc.contributor.authorWirth, G.
dc.contributor.authorGrasser, T.
dc.contributor.authorGroeseneken, Guido
dc.date.accessioned2021-10-22T00:51:41Z
dc.date.available2021-10-22T00:51:41Z
dc.date.issued2014
dc.identifier.issn1063-8210
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/23602
dc.sourceIIOimport
dc.titleUse of SSTA tools for evaluating BTI impact on combinational circuits
dc.typeJournal article
dc.contributor.imecauthorKaczer, Ben
dc.contributor.imecauthorGroeseneken, Guido
dc.contributor.orcidimecKaczer, Ben::0000-0002-1484-4007
dc.date.embargo9999-12-31
dc.source.peerreviewyes
dc.source.beginpage280
dc.source.endpage285
dc.source.journalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
dc.source.issue2
dc.source.volume22
dc.identifier.urlhttp://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6466436&tag=1
imec.availabilityPublished - open access


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