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Spike anneal peak temperature impact on 1T-DRAM retention time

dc.contributor.authorNissimoff, Albert
dc.contributor.authorMartino, Joao A.
dc.contributor.authorAoulaiche, Marc
dc.contributor.authorVeloso, Anabela
dc.contributor.authorWitters, Liesbeth
dc.contributor.authorSimoen, Eddy
dc.contributor.authorClaeys, Cor
dc.date.accessioned2021-10-22T04:19:19Z
dc.date.available2021-10-22T04:19:19Z
dc.date.issued2014
dc.identifier.issn0741-3106
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/24325
dc.sourceIIOimport
dc.titleSpike anneal peak temperature impact on 1T-DRAM retention time
dc.typeJournal article
dc.contributor.imecauthorVeloso, Anabela
dc.contributor.imecauthorWitters, Liesbeth
dc.contributor.imecauthorSimoen, Eddy
dc.contributor.orcidimecSimoen, Eddy::0000-0002-5218-4046
dc.source.peerreviewyes
dc.source.beginpage639
dc.source.endpage641
dc.source.journalIEEE Electron Device Letters
dc.source.issue6
dc.source.volume35
dc.identifier.urlhttp://ieeexplore.ieee.org/xpl/abstractAuthors.jsp?reload=true&arnumber=6811203&sortType%3Dasc_p_Sequence%26filter%3DAND(p_Publi
imec.availabilityPublished - imec


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