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Different stress techniques and their efficiency on triple-gate SOI n-MOSFETs

dc.contributor.authorBuhler, Rudolf
dc.contributor.authorAgopian, Paula GD
dc.contributor.authorCollaert, Nadine
dc.contributor.authorSimoen, Eddy
dc.contributor.authorClaeys, Cor
dc.contributor.authorMartino, Joao
dc.date.accessioned2021-10-22T18:36:17Z
dc.date.available2021-10-22T18:36:17Z
dc.date.issued2015
dc.identifier.issn0038-1101
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/25028
dc.sourceIIOimport
dc.titleDifferent stress techniques and their efficiency on triple-gate SOI n-MOSFETs
dc.typeJournal article
dc.contributor.imecauthorCollaert, Nadine
dc.contributor.imecauthorSimoen, Eddy
dc.contributor.orcidimecCollaert, Nadine::0000-0002-8062-3165
dc.contributor.orcidimecSimoen, Eddy::0000-0002-5218-4046
dc.source.peerreviewyes
dc.source.beginpage209
dc.source.endpage215
dc.source.journalSolid-State Electronics
dc.source.volume103
dc.identifier.urlhttp://www.sciencedirect.com/science/article/pii/S0038110114001956
imec.availabilityPublished - imec


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