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Bias Temperature Instability in CMOS Digital Circuits from Planar to FinFET Nodes

dc.contributor.authorKukner, Halil
dc.date.accessioned2021-10-22T20:16:03Z
dc.date.available2021-10-22T20:16:03Z
dc.date.issued2015-04
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/25498
dc.sourceIIOimport
dc.titleBias Temperature Instability in CMOS Digital Circuits from Planar to FinFET Nodes
dc.typePHD thesis
dc.date.embargo9999-12-31
dc.source.peerreviewno
dc.contributor.thesisadvisorLauwereins, Rudy
dc.contributor.thesisadvisorVan der Perre, Liesbet
dc.identifier.urlhttps://limo.libis.be/primo-explore/fulldisplay?docid=LIRIAS1734373&context=L&vid=Lirias&search_scope=Lirias&tab=default_tab&lang=en_US&fromSitemap=1
imec.availabilityPublished - open access


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