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Technology/circuit/system co-optimization and benchmarking for multilayer graphene interconnects at sub-10-nm technology node

dc.contributor.authorPan, Chenyun
dc.contributor.authorRaghavan, Praveen
dc.contributor.authorCeyhan, Ahmet
dc.contributor.authorCatthoor, Francky
dc.contributor.authorTokei, Zsolt
dc.contributor.authorNaeemi, Azad
dc.date.accessioned2021-10-22T21:37:29Z
dc.date.available2021-10-22T21:37:29Z
dc.date.issued2015
dc.identifier.issn0018-9383
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/25729
dc.sourceIIOimport
dc.titleTechnology/circuit/system co-optimization and benchmarking for multilayer graphene interconnects at sub-10-nm technology node
dc.typeJournal article
dc.contributor.imecauthorCatthoor, Francky
dc.contributor.imecauthorTokei, Zsolt
dc.contributor.orcidimecCatthoor, Francky::0000-0002-3599-8515
dc.date.embargo9999-12-31
dc.source.peerreviewyes
dc.source.beginpage1530
dc.source.endpage1536
dc.source.journalIEEE Transactions on Electron Devices
dc.source.issue5
dc.source.volume62
dc.identifier.urlhttp://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=7061953
imec.availabilityPublished - open access


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