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A DfT architecture and tool flow for 3D-SICs with test data compression, embedded cores, and multiple towers

dc.contributor.authorPapameletis, Christos
dc.contributor.authorKeller, Brion
dc.contributor.authorChickermane, Vivek
dc.contributor.authorHamdioui, Said
dc.contributor.authorMarinissen, Erik Jan
dc.date.accessioned2021-10-22T21:39:28Z
dc.date.available2021-10-22T21:39:28Z
dc.date.issued2015
dc.identifier.issn2168-2355
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/25734
dc.sourceIIOimport
dc.titleA DfT architecture and tool flow for 3D-SICs with test data compression, embedded cores, and multiple towers
dc.typeJournal article
dc.contributor.imecauthorMarinissen, Erik Jan
dc.contributor.orcidimecMarinissen, Erik Jan::0000-0002-5058-8303
dc.date.embargo9999-12-31
dc.source.peerreviewyes
dc.source.beginpage40
dc.source.endpage48
dc.source.journalIEEE Design & Test
dc.source.issue4
dc.source.volume32
dc.identifier.urlhttp://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=7089208
imec.availabilityPublished - open access


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