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Demonstrating HW-SW transient error mitigation on the single-chip cloud computer data plane

dc.contributor.authorRodopoulos, Dimitrios
dc.contributor.authorPapanikolaou, A.
dc.contributor.authorCatthoor, Francky
dc.contributor.authorSoudris, Dimitrios
dc.date.accessioned2021-10-22T22:19:38Z
dc.date.available2021-10-22T22:19:38Z
dc.date.issued2015
dc.identifier.issn1063-8210
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/25830
dc.sourceIIOimport
dc.titleDemonstrating HW-SW transient error mitigation on the single-chip cloud computer data plane
dc.typeJournal article
dc.contributor.imecauthorCatthoor, Francky
dc.contributor.orcidimecCatthoor, Francky::0000-0002-3599-8515
dc.date.embargo9999-12-31
dc.source.peerreviewyes
dc.source.beginpage507
dc.source.endpage519
dc.source.journalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
dc.source.issue3
dc.source.volume23
dc.identifier.urlhttp://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6784042
imec.availabilityPublished - open access


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