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Impact of on- and off-chip protection on the transient-induced latch-up sensitivity of CMOS IC

dc.contributor.authorScholz, Mirko
dc.contributor.authorChen, Shih-Hung
dc.contributor.authorHellings, Geert
dc.contributor.authorLinten, Dimitri
dc.contributor.authorGroeseneken, Guido
dc.date.accessioned2021-10-23T14:41:30Z
dc.date.available2021-10-23T14:41:30Z
dc.date.issued2016-02
dc.identifier.issn0026-2714
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/27280
dc.sourceIIOimport
dc.titleImpact of on- and off-chip protection on the transient-induced latch-up sensitivity of CMOS IC
dc.typeJournal article
dc.contributor.imecauthorChen, Shih-Hung
dc.contributor.imecauthorHellings, Geert
dc.contributor.imecauthorLinten, Dimitri
dc.contributor.imecauthorGroeseneken, Guido
dc.contributor.orcidimecHellings, Geert::0000-0002-5376-2119
dc.contributor.orcidimecLinten, Dimitri::0000-0001-8434-1838
dc.contributor.orcidimecGroeseneken, Guido::0000-0003-3763-2098
dc.identifier.doi10.1016/j.microrel.2015.12.009
dc.source.peerreviewyes
dc.source.beginpage53
dc.source.endpage58
dc.source.journalMicroelectronics Reliability
dc.source.volume57
dc.identifier.urlhttp://www.sciencedirect.com/science/article/pii/S0026271415302560
imec.availabilityPublished - imec


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