III-V Nanowire Epitaxy for Ultimate Logic Device Scaling
| dc.contributor.author | Liu, Ziyang | |
| dc.date.accessioned | 2021-10-24T08:07:11Z | |
| dc.date.available | 2021-10-24T08:07:11Z | |
| dc.date.issued | 2017-10 | |
| dc.identifier.uri | https://imec-publications.be/handle/20.500.12860/28840 | |
| dc.source | IIOimport | |
| dc.title | III-V Nanowire Epitaxy for Ultimate Logic Device Scaling | |
| dc.type | PHD thesis | |
| dc.date.embargo | 9999-12-31 | |
| dc.source.peerreview | no | |
| dc.contributor.thesisadvisor | Heyns, Marc | |
| dc.identifier.url | https://lirias.kuleuven.be/handle/123456789/591999 | |
| imec.availability | Published - open access |