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Doping-free complementary logic gates enabled by two-dimensional polarity-controllable transistors

dc.contributor.authorResta, Giovanni
dc.contributor.authorBalaji, Yashwanth
dc.contributor.authorLin, Dennis
dc.contributor.authorRadu, Iuliana
dc.contributor.authorCatthoor, Francky
dc.contributor.authorGaillardon, Pierre-Emmanuel
dc.contributor.authorDe Micheli, Giovanni
dc.date.accessioned2021-10-26T02:29:03Z
dc.date.available2021-10-26T02:29:03Z
dc.date.issued2018
dc.identifier.issn1936-0851
dc.identifier.urihttps://imec-publications.be/handle/20.500.12860/31651
dc.sourceIIOimport
dc.titleDoping-free complementary logic gates enabled by two-dimensional polarity-controllable transistors
dc.typeJournal article
dc.contributor.imecauthorBalaji, Yashwanth
dc.contributor.imecauthorLin, Dennis
dc.contributor.imecauthorRadu, Iuliana
dc.contributor.imecauthorCatthoor, Francky
dc.contributor.orcidimecRadu, Iuliana::0000-0002-7230-7218
dc.contributor.orcidimecCatthoor, Francky::0000-0002-3599-8515
dc.source.peerreviewyes
dc.source.beginpage7039
dc.source.endpage7047
dc.source.journalACS Nano
dc.source.issue7
dc.source.volume12
dc.identifier.urlhttps://doi.org/10.1021/acsnano.8b02739
imec.availabilityPublished - imec


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